It is known that semiconductor devices can be constructed that have bi-stable states, that is, whose conductance can be switched between a high and a low state (and vice-versa) by a programming voltage, and that will remain in such high or low state even after the programming voltage is removed. These are used as “non-volatile” memory devices when it is desired to retain information represented by the high or low state even when the power to the device or circuit is turned off. FIG. 1 illustrates prior art MOS device 20 having such capability. Device 20 comprises semiconductor substrate 21 (e.g., of Si) having a first conductivity type, in which are located source region 22 with contact 23 and drain region 24 with contact 25. Source region 22 and drain region 24 are of a second opposite conductivity type. Channel region 27 extends between source region 22 and drain region 24 at surface 30. Above surface 30 between source region 22 and drain region 24 is gate structure 28. Buffer regions 29 laterally separate gate structure 28 from source-drain contacts 23, 25. Buffer regions 29 are also referred to as lateral spacers 29. Field oxide regions 32 conveniently extend from surface 30 into substrate 21 laterally outside source-drain contacts 23, 25. Starting at surface 30 and proceeding upward (i.e., vertically in FIG. 1) gate structure or stack 28 comprises thin gate dielectric layer 281 (e.g., SiO2) on which has been formed nano-crystals 285, then second dielectric layer 282 (e.g., also of SiO2), and then gate conductor layer 283, of for example poly-Si or other conductors. Nano-crystals 285 can be made of Si, SiGe, metals, other conductors and combinations thereof and, as used herein, the term “nano-crystals” is intended to include nano-structures of these and other conductive materials whether crystalline or not. Nano-crystals 285 provide localized electron trap sites. When a sufficiently large programming voltage is applied between substrate 21, source 22, or drain 24 on one side and gate conductor 283 on the other, electron tunneling or other field assisted conduction can occur through thin gate dielectric layer 281 to or from substrate 21 and nano-crystals 285. Thus, charge can be placed on or removed from nano-crystals 285. Charge placed on nano-crystals 285 remains there even when the programming voltage is removed. It is recognized by those skilled in the art that nano-crystals 285 have the function of a floating gate used in conventional non-volatile memory devices. The trapped charge has the effect of providing an effective gate bias that can place device 20 in a conducting or non-conducting state. This state persists even after the programming voltage is removed. Thus, devices of the type illustrated in FIG. 1 can function as non-volatile memory devices. However, such devices suffer from a variety of limitations well known in the art. Non-limiting examples are that: (i) the number of write-erase cycles is more limited than desired, (ii) there can be slow leakage of the charge from nano-crystals 285, and (iii) there can be a gradual drift of the device electrical properties as the device ages.
There is an ongoing need for semiconductor devices that exhibit non-volatile bi-stable or multi-stable behavior but which mitigate or overcome these and other limitations of the prior art. Accordingly, it is desirable to provide an improved device structure and method for non-volatile semiconductor memory devices. In addition, it is desirable that the changes in device structure and method of fabrication used to improve the devices be compatible with or involve little or no change in existing device manufacturing techniques. Furthermore, other desirable features and characteristics of the various embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.